1. Field of the Invention
The present invention relates to the field of analog signal processing, and in particular to squaring an input signal by using field effect transistors operated in the saturation region to obtain an output signal that is proportional to the square of the input signal.
2. Description of the Related Art
In the field of analog signal processing very often a square output of an input signal is required. Since field effect transistors provide a plurality of advantages over bipolar transistors, for example, with respect to power consumption, a great deal of effort has been made in developing analog circuits that include squaring circuitry using field effect transistors instead of bipolar transistors. In most of these analog circuits, such as in four-quadrant multipliers, for a squaring stage of the circuit, the square relationship of the drain current IDS with respect to the difference of the gate-source voltage VGS and the threshold voltage of a field effect transistor VTh is employed when operated in the saturation region. The saturation region of a field effect transistor is defined as the region in which the voltage applied to the drain-source terminals VDS is higher than the difference of VGS and VTh. In this operation mode, the drain current is given by the following equation:
IDS=K (VGSxe2x88x92VTh)2, 
where K=xc2xd xcexc0COX(W/L) is the transconductance parameter, wherein xcexc0 is the effective surface mobility, COX is the gate capacitance per unit area and W/L is the aspect ratio of the transistor channel width W and the transistor channel length L. Despite this inherent square relationship between the drain-source current and the gate-source voltage, it is nevertheless difficult to realize a simple and efficient circuit providing a pure square output signal, wherein variation of transistor characteristics does not adversely affect operation of the circuit.
The document xe2x80x9cAn MOS Four-Quadrant Analog Multiplier Using Simple Two-Input Squaring Circuits with Source Followersxe2x80x9d by Ho-Jun Song and Choong-Ki Kim, published in IEEE Journal of Solid-State Circuits, Vol. 25, No. 3, June 1990, describes a four-quadrant multiplier based on the square-algebraic identity (V1+V2)2xe2x88x92(V1xe2x88x92V2)2=4V1V2 and using the above-mentioned square law of MOS transistors. The multiplier includes circuits for squaring the sum and the difference of two differential input signals. Each squaring circuit comprises two MOS transistors acting as source followers, two so-called squaring transistors and a load, such as a resistor. However, the squaring circuits in this document require that the aspect ratio of the source followers be much larger than the aspect ratio of the squaring transistors, and that the drain current of the squaring transistors be less than a bias current flowing through the squaring transistors and the source followers, so that the gate-to-source voltage drop of the source followers can be regarded as constant. The constant gate-to-source voltage drop is necessary to obtain the required squaring of the sum and the difference, respectively, of the input signals. Moreover, it is difficult to provide MOS transistors that fulfill the condition regarding their aspect ratio mentioned above.
The document xe2x80x9cA Four-Quadrant CMOS Analog Multiplier for Analog Neural Networks,xe2x80x9d by N. Saxena and J. J. Clark, published in IEEE Journal of Solid-State Circuits, Vol. 29, No. 6, June 1994 describes a four-quadrant analog multiplier with 5 n-MOS field effect transistors and two current mirrors. The operation of the four-quadrant multiplier is based on the algebraic identity (V1+V2)2xe2x88x92V12xe2x88x92V22=2V1V2 and provides an output current Iout=xe2x88x922K Vin1 Vin2. The multiplier, however, does not provide a squared signal of the input signals, but instead creates respective drain currents in the transistors that are proportional to the square of the differences of the input voltages and the threshold voltages of the transistors. Since the MOS transistors are identical, summation of the individual drain currents eliminates the threshold voltages and produces an output voltage that is given by Iout=xe2x88x922K Vin1 Vin2.
The document xe2x80x9cA CMOS Four-Quadrant Analog Multiplier with Single-Ended Voltage Output and Improved Temperature Performance,xe2x80x9d by Z. Wang, published in IEEE Journal of Solid-State Circuits, Vol. 26, No. 9, September 1991 discloses a multiplier consisting of a differential transconductor based on the square-difference technique, a scaled floating-voltage pair generator, an MOS resistor, and a bias generator. The MOS transconductor uses 2 cross-coupled pairs of MOS transistors operated in the saturation region. A floating bias voltage is applied between the gates of a respective pair of transistors. The circuit provides an output current that is proportional to the input voltage times the bias voltage, rather than an output current that is proportional to the square of the input signal.
Since producing the square of an input signal is required for a plurality of electronic devices and methods, such as measuring the root mean square value of any type of signal, there exists a need for an improved square multiplier providing fast signal performance while exhibiting low power consumption.
According to one aspect of the present invention, a field effect transistor (FET) square multiplier for squaring an input signal is provided, comprising a first field effect transistor formed on a substrate and having a gate, a source, a drain and a channel, the gate of the first field effect transistor connected to receive a sum of the input signal and a reference signal. The FET square multiplier also comprises a second field effect transistor formed on the substrate and having a gate, a source, a drain and a channel, the gate of the second field effect transistor connected to receive a difference of the input signal and the reference signal, wherein the first and second field effect transistors have a first aspect ratio of channel width to channel length, a first gate insulation layer capacitance per unit area and a first charge carrier mobility. The FET square multiplier also comprises a third field effect transistor formed on the substrate and having a gate, a source, a drain and a channel, the gate of the third field effect transistor connected to receive the reference signal, the third field effect transistor having a second aspect ratio of channel width to channel length, a second gate insulation layer capacitance per unit area and a second charge carrier mobility. Additionally, the FET square multiplier comprises a constant current source connected to the source of the first, second and third field effect transistors, respectively; wherein the drain of the first field effect transistor is connected to the drain of the second field effect transistor, and a parameter value defined as the product of aspect ratio, gate insulation layer capacitance per unit area and charge carrier mobility of the third field effect transistor is two times the corresponding parameter value of the first and second field effect transistors, wherein the field effect transistor square multiplier is adapted to provide a current I1 at a common node connected to the drain of the first and second field effect transistors and a current I2 at the drain of the third field effect transistor, wherein a difference of I1 and I2 is proportional to the square of the input signal when the first, second and third field effect transistors are operated in the saturation region.
According to another aspect of the present invention, an analog signal processing unit is provided, the analog signal processing unit comprising a plurality of square multipliers cooperatively connected to form an output signal in response to at least one input signal, the output signal representing a predefined function of the at least one input signal. In the analog signal processing unit each of the square multipliers includes a first field effect transistor formed on a substrate and having a gate, a source, a drain and a channel, the gate of the first field effect transistor connected to receive a sum of the at least one input signal and a reference signal. Each of the square multipliers also comprises a second field effect transistor formed on the substrate and having a gate, a source, a drain and a channel, the gate of the second field effect transistor connected to receive a difference of the at least one input signal and the reference signal, wherein the first and second field effect transistors have a first aspect ratio of channel width to channel length, a first gate insulation layer capacitance per unit area and a first charge carrier mobility. Each of the square multipliers further comprises a third field effect transistor formed on the substrate and having a gate, a source, a drain and a channel, the gate of the third field effect transistor connected to receive the reference signal, the third field effect transistor having a second aspect ratio of channel width to channel length, a second gate insulation layer capacitance per unit area and a second charge carrier mobility. Additionally, each of the square multipliers comprises a constant current source connected to the source of the first, second and third field effect transistors, respectively, wherein the drain of the first field effect transistor is connected to the drain of the second field effect transistor, and a parameter value defined as the product of aspect ratio, gate insulation layer capacitance per unit area and charge carrier mobility of the third field effect transistor is two times the corresponding parameter value of the first and second field effect transistors, each of the field effect transistor square multipliers adapted to provide a current I1 at a common node connected to the drain of the first and second field effect transistors and a current I2 at the drain of the third field effect transistor element, wherein a difference of I1 and I2 is proportional to the square of the at least one input signal. The analog signal processing unit further comprises a common current mirror connected to each of the plurality of square multipliers to form an output current representing the output signal.
According to a further aspect of the present invention, a method for squaring an input signal with a plurality of field effect transistors is provided, the method comprising providing a first field effect transistor having a gate, a source, a drain and a channel, the gate of the first field effect transistor connected to receive a sum of the input signal and a reference signal. The method also comprises providing a second field effect transistor having a gate, a source, a drain and a channel, the gate of the second field effect transistor connected to receive a difference of the input signal and the reference signal, wherein the first and second field effect transistors having a first aspect ratio of channel width to channel length, a first gate insulation layer capacitance per unit area and a first charge carrier mobility. The method further comprises providing a third field effect transistor having a gate, a source, a drain and a channel, the gate of the third field effect transistor connected to receive the reference signal, the third field effect transistor having a second aspect ratio of channel width to channel length, a second gate insulation layer capacitance per unit area and a second charge carrier mobility. Furthermore, the method comprises providing a constant current source connected to the source of the first, second and third field effect transistors, respectively, wherein the drain of the first field effect transistor is connected to the drain of the second field effect transistor, and a parameter value defined as the product of aspect ratio, gate insulation layer capacitance per unit area and charge carrier mobility of the third field effect transistor is two times the corresponding parameter value of the first and second field effect transistors. Additionally, the method comprises connecting the drains of the first and second field effect transistors to a first voltage and connecting the drain of the third field effect transistor to a second voltage, and initiating a current I through the constant current source to maintain the first, second and third field effect transistors, respectively, in the saturation region, wherein a difference of a current I1 at a common node connected to the drain of the first and second field effect transistors and a current I2 through the third field effect transistor is proportional to the square of the input signal.
The present invention allows the formation of a square multiplier with a minimum number of field effect transistors formed on a common substrate. Accordingly, a fast and power-saving device can be made, requiring a minimum chip area so that these square multipliers can easily be implemented in a variety of signal processing circuits even if a large number of multipliers is necessary. The field effect transistors of the multiplier are formed such that one of the transistors exhibits a transconductance value that is twice the transconductance value of each of the other two transistors. Therefore, the transistors may easily be formed in a common manufacturing process wherein, for example, the transistor channel width of one transistor is selected as twice the width of the other two transistors. The corresponding processes for defining the dimensions of the channel width are well-controllable in the manufacturing process, such as an MOS process, and, hence, the required width-to-width relationship of the first and second field effect transistors with the third field effect transistor can be obtained with high precision, wherein a high degree of uniformity of the remaining parameters of the transistors, such as gate capacitance per unit area and charge carrier mobility is insured. Similarly, and/or alternatively, the channel length may accordingly be adapted to provide the required double-size aspect ratio. Furthermore, in some cases it may be advantageous to change the gate capacitance per unit area of the transistors and/or the charge carrier mobility to obtain the required transconductance relationship for proper operation of the present square multiplier. Preferably, the aspect ratios of the first, second and third transistors, however, are adapted to meet the requirement of a doubled transconductance value of the third transistor.
In a further embodiment of the present invention, substantially identical field effect transistors are provided on a common substrate wherein two or more transistors are cooperatively operated so as to form one or more of each of the first, second and third field effect transistors having the required transconductance relationship. This may be accomplished in that two or more transistors may be electrically connected in series and/or in parallel to form any or all of the first and/or the second and/or the third field effect transistors.
Moreover, a square multiplier according to the present invention may comprise a current mirror, which may be formed of two transistor elements to provide an output stage for outputting the difference of the currents I1 and I2, representing the square of the input signal, wherein the output current signal allows a simple addition of output signals of a plurality of square multipliers. Moreover, two or more square multipliers may be connected together to form a functional unit that outputs a predefined function of one or more input signals when creation of the defined output function necessitates a plurality of squaring operations. The functional unit may further comprise a plurality of current mirrors, or, alternatively, a single common current mirror connected to each of the two or more square multipliers to provide a combined current signal representing the required output function.